1. Field of the Invention
The present invention relates to a method of manufacturing a bonding substrate composed of two semiconductor substrates bonded together, and more particularly to a method of manufacturing a so-called bonding SOI (Silicon on Insulator) substrate in which two silicon monocrystalline substrates are bonded together via a silicon oxide film.
2. Description of the Related Art
There have been known various methods of manufacturing a bonding SOI substrate in which two silicon monocrystalline substrates are bonded together via a silicon oxide film. In the method shown, for example, in Japanese Patent Publication (kokoku) 5-46086, an oxide film is formed on at least one of two substrates; the two substrates are brought into close contact with each other with no foreign substance being interposed between the joint surfaces thereof; and the substrates are then subjected to heat treatment at a temperature of about 200.degree. to 1200.degree. C. in order to increase bonding strength.
Since a bonding substrate whose joint strength has been increased by means of heat treatment can undergo a subsequent grinding and polishing process, the thickness of one substrate on which devices are to be fabricated can be reduced to a desired thickness through grinding or polishing in order to obtain an SOI layer for formation of semiconductor elements.
However, it is known that a bonding substrate manufactured in the above-described manner has an unjoined portion in an area extending about 1-3 mm from the peripheral edge of the substrate. In order to remove such an unjoined portion, there have been developed various techniques such as those shown in Japanese Patent Application Laid-Open (kokai) Nos. 3-89519 and 4-263425.
Although these methods can remove such an unjoined portion, in subsequent processes resultant substrates cannot be handled in the same manner as ordinary wafers. That is, since the peripheral portion of one substrate on which devices are to be fabricated (bond wafer) is ground to reach the other substrate which serves as a support substrate (base wafer), the shape of the base wafer changes greatly from the original shape, making it difficult to handle the resultant wafer in the same manner as used for ordinary wafers.
There have also been proposed methods of manufacturing a bonding SOI substrate that do not involve the above-described problem, such as those described in Japanese Patent Application Laid-Open (kokai) Nos. 3-250616 and 64-89346. In the method disclosed in Japanese Patent Application Laid-Open No. 3-250616, a piece of masking tape is applied to a wafer to cover the entire wafer except the peripheral portion, and then etching is performed in order to remove the unjoined portion at the periphery of the wafer. In the method disclosed in Japanese Patent Application Laid-Open No. 64-89346, the entire peripheral portion of a bonded wafer is removed through etching.
Further, Japanese Patent Application Laid-Open (kokai) No. 7-45485 discloses another method of manufacturing a boding substrate. In this method, the peripheral portion of a bonding wafer is removed through grinding to a degree such that damage does not reach the base wafer; the unjoined portion at the periphery of the bonding wafer is then completely removed through etching; and the bonding wafer is ground and/or polished to yield a thin film having a desired thickness.
The above-described methods can remove an unjoined portion of a bonding wafer without changing the shape of the base wafer.
Meanwhile, accompanying a recent increase in the degree of integration and speed of semiconductor devices, demand exists to further reduce the thickness of an SOI layer. Recently, there has arisen demand for an ultra-thin SOI layer having a thickness of 1 .mu.m or less. Accordingly, in order to manufacture a bonding substrate having such an ultra-thin SOI layer, the bond wafer must be machined to a thickness of 0.1 micron or less with accuracy of at least .+-.0.01 micron.
In order to realize accurate film machining to 0.1.+-.0.01 micron, there has been developed a technique, a so-called PACE (plasma assisted chemical etching) method, as disclosed in Japanese Patent Application Laid-Open (kokai) No. 5-160074. The PACE method is a method for making the thickness of a thin film uniform through vapor-phase etching. In this method, thickness distribution of a silicon layer to be made uniform is measured in order to create a map of the thickness distribution, and a thicker portion is locally removed through vapor-phase etching that is numerically controlled in accordance with the map. This method enables manufacture of an ultra-thin film having a highly uniform thickness.
However, in a method of manufacturing a bonding substrate having a step of removing an unjoined portion, if the surface of a thin film is subjected to vapor-phase etching in order to yield an ultra-thin SOI layer having a highly uniform thickness, a groove, trench, depression, or the like (hereinafter generically referred to as a "groove") is formed in the surface of an unjoined portion of a support substrate (base wafer). The groove allows photo resist to remain in a subsequent device process or causes improper focusing in an exposure process.